1. Technical Field
The present invention relates generally to microprocessor systems and in particular to the testing of microprocessor systems. Still more particularly, the present invention relates to the testing of microprocessor systems in an accelerated simulation environment using cache and replacement management tables.
2. Description of the Related Art
With the increasing complexity of microprocessor designs, a parallel increase in the resources devoted to verifying a design's correctness has also been made. The number of potential logic combinations on a microprocessor has far exceeded the number of atoms in the universe, and thus, ensuring the validity of a microprocessor's design is truly a Herculean task. Numerous methodologies are employed to tackle this seemingly insurmountable problem. One of the primary methods is cycle simulation. Cycle simulation uses a software model of a hardware design to simulate the cycle by cycle state transitions of a synchronous design. The current state of the art cycle simulators are able to simulate tens or possibly hundreds of cycles per second, which corresponds to several minutes of microprocessor operations. Thus, even using contemporary cycle simulators, the number of cycles that one can hope to simulate before fabrication only corresponds to a minimal period (i.e., the several minutes) of actual microprocessor operation. Because of finite resources, the state space one is able to cover with cycle simulation is limited.
To improve the coverage provided by cycle simulation, formal verification is also frequently employed. Formal verification proves mathematically that the hardware design is functioning as intended. While formal verification is extremely effective, this method requires significant resources to support, and not all parts of a design are practical to verify using this methodology. Typically, only small parts of a design can be verified formally because designs are often too big or too complex to fully employ formal verification.
Accelerated simulation is yet another methodology with its own pros and cons used to verify a microprocessor's validity. Accelerated simulation refers to the process of mapping the synthesizable portion of the design into a hardware platform to increase performance by evaluating the high definition language (HDL) constructs in parallel. The method does not map the remaining portions of the simulation into hardware but runs them in a software simulator. The software simulator works with the hardware platform to exchange simulation data. Removing most of the simulation events from the software simulator and evaluating them in parallel improve performance. Accelerated simulation makes use of an FPGA or other hardware to drastically increase the speed of simulation. Accelerated simulation is orders of magnitude faster than cycle simulation, achieving simulation speeds of thousands or tens of thousands of cycles per second. To achieve these drastic increases in performance, accelerated simulation foregoes much of the checking used in either formal verification or cycle simulation. As a result, the checking is less thorough and failures are much harder to debug. Because of this lack of checking, additional algorithms and methods that enable a subsequent “self check” are frequently required to be executed following the accelerated simulation.
In the light of the above limitations with conventional accelerated simulation techniques, the present invention provides an improved verification methodology to extend the debugging capabilities of accelerated simulation.